As is known in the art, Microelectromechanical systems (MEMS) are integrated micro devices or systems combining electrical and mechanical components. MEMS devices may be fabricated using, for example, standard integrated circuit batch processing techniques. Exemplary applications for MEMS devices include sensing, controlling, and actuating on the micro scale. Such MEMS devices may function individually or in arrays to generate effects on a macro scale.
As is also known in the art, many MEMS devices require a hermetically sealed environment in order to attain maximum performance. This could be a vacuum environment, a controlled pressure environment or a controlled gas environment. The package environment also provides protection and an optimal operating environment for the MEMS device. Specific examples of these MEMS devices include infrared MEMS such as bolometers, sometimes referred to as microbolometers, certain inertial MEMS such as gyros and accelerometers, and optical mechanical devices such as moving mirror arrays. Previously, MEMS devices have been individually packaged in vacuum compatible packages alter fabrication and dicing of the MEMS device wafer. Often, however, the cost of packaging MEMS devices in traditional metal or ceramic packages may be on the order of about 10 to 100 times the device fabrication cost. This is especially true if a vacuum is required in the package.
Over the years, various types of infrared detectors have been developed. Many include a substrate having thereon a focal plane array, the focal plane array including a plurality of detector elements (detector devices) that each correspond to a respective pixel. The substrate contains an integrated circuit which is electrically coupled to the detector elements, and which is commonly known as a read out integrated circuit (ROIC) and which is used to integrate the signal from each detector element and multiplex the signals off the chip with appropriate signal conditioning and processing.
As is the case with certain microelectromechanical (MEMS) devices, bolometers may need to be hermetically packaged in vacuum or other controlled environment conditions for best performance. Exemplary requirements for the packaging of bolometer arrays include reliable hermetic sealing capable of maintaining a high vacuum for an extended period of time, the integration of IR window material with good infrared transmission, and high yield/low cost packaging. Both the reliability and the cost of MEMS devices depend upon encapsulation (packaging) techniques chosen. For MEMS based bolometers, packaging may be done at the chip level or at the wafer level. A common way of packaging in this instance is to fabricate a protective, IR-transmitting cap wafer, or Window Cap Wafer (WCW), and bond it to an exposed surface of the semiconductor substrate, or device wafer, containing the active IR detector bolometer areas prior to dicing. The cap wafer, sometimes, also referred to as a window or lid structure, is formed with cavities therein such that when the cap wafer is flipped and bonded to the device wafer, the cavities provide sufficient clearance to accommodate and protect the MEMS devices therein as described in U.S. Pat. No. 5,701,008, entitled Integrated infrared microlens and gas molecule getter grating in a vacuum package, inventors Ray et al., issued Dec. 23, 1997. As described therein, and referring to FIGS. 1 and 2, a package assembly is shown having a readout integrated circuit (ROIC) substrate 2 of a semiconductor material, preferably silicon. An IR detector array 14 is positioned on the substrate 2 and includes a plurality of individual detector elements, also called pixels, 6. Although FIG. 2 shows only a 5×6 rectangular array of detector pixels 6 in detector region 10, it is understood that a typical IR integrated circuit generally includes a planar IR detector array with up to several hundred or even thousand by several hundred or even thousand pixels 6. In most commercial applications, IR detectors are usually uncooled and detect the intensity of IR radiation by sensing increases in temperature which result from the heat imparted to the detectors by the IR radiation. A typical example of an uncooled IR detector is a vanadium oxide (VOx) microbolometer (MB), in which a plurality of individual detectors are usually formed in an array on the ROIC substrate 2 by conventional semiconductor manufacturing processes. The MB array detects IR radiation by sensing the IR-generated heat, and is also called a focal plane array (FPA) or a sensor chip assembly (SCA). The substrate 2 is an integrated circuit used to process the signal produced by the bolometers. In this case the bolometer is a microbridge resistor that changes its resistance when its temperature changes. The incoming radiation causes a change in the temperature of the microbridge. Although other semiconductor materials such as Si may be used, VOx is a commonly available and cost effective material that is used in most commercial IR detection applications.
As described in the above-referenced U.S. Pat. No. 5,701,008, the vacuum-sealed assembly includes a hermetic seal 8 surrounding the IR detector array to seal off the detector array from the atmosphere. The seal 8 can be, for example, an indium, gold-tin, or other solder, with the height of the seal precisely controlled when it is deposited on the substrate 2 or preferably wafer 10. The seal 8 supports a second substrate, a cap wafer, here an IR transparent window 10, here for example, silicon so that with wafer level packaging the window wafer 10 must have a compatible thermal expansion coefficient with the FPA wafer which is also silicon. The wafer 10 may include a gettering material, not shown formed, on a predetermined region of the surface of the wafer 10 having a predetermined surface area as described in the above-referenced U.S. Pat. No. 5,701,008.
As is also known in the art, Wafer Level Packaging (WLP) was developed to address the high cost of packaging of MEMS by eliminating the traditional packages. One such WLP package is described in U.S. Pat. No. 6,521,477, entitled Vacuum package fabrication of integrated circuit components, inventors Gooch et al., issued Feb. 18, 2003. In one WLP process, two wafers may be bonded together using a joining material to yield bonded wafers. For example, one of the wafers is a semiconductor (for example, silicon) device wafer having therein the detector devices in a detector region of the wafer, the detector region being disposed in a central interior region of the device wafer along with a read out integrated circuit (ROIC) which is bonded to the other wafer, the lid wafer using an seal metal ring of solder disposed about the detector region of the device wafer. After forming the devices in the semiconductor wafer, the wafer includes a thin overglass layer, such as silicon nitride or silicon oxynitride (SiON). The seal ring metal is fainted using conventional photolithographic processing to form a bottom layer of titanium, which serves as a substrate adhesion layer to the ROIC overglass, then an intermediate layer of Nickel, which serves as a diffusion barrier followed by a layer of gold to prevent oxide formation and enhance solder bonding, which will subsequently be referred to as the “seal ring”. A similar set of layers is formed on the lid wafer which provides a mating surface for the solder seal between the device and lid wafer. Following the formation of the seal ring, solder, for example Au 80% and Sn 20%, is applied to either or both the device and lid wafer.
While the WLP technique described provides an effective package, the inventors have recognized that because the difference between the thermal coefficient of expansion of the AuSn solder and the semiconductor device wafer, stresses may build up at high stress region as shown in FIG. 3 wherein the edge of the seal ring contacts the device or ROIC wafer. These stresses may cause unwanted cracks to develop in the overglass and underlying structure of the device or ROIC wafer as shown in FIG. 3. These cracks can break the interlayered dielectric layer (ILD) and metal interconnecting traces in the ILD of the ROIC leading to failure.
More particularly, the inventors have recognized that in the prior art the seal ring metal stack (about 0.5 um thick) and the solder (up to 11 um thick) have a coincident edge. As the solder cools below its ˜280 degree Centigrade melting temperature the solder shrinks faster than the underlying seal ring and ROIC (solder CTE ˜16 ppm, silicon CTE ˜3 ppm), and the solder is very stiff (AuSn solder has a high Young's modulus) so it cannot deform to relieve the stress. The shrinkage of the solder layer tends to pull on the edge of the solder joint, which is the source of a stress point r and the resulting crack at the edge of the joint. Simply increasing the thickness of the titanium (Ti) portion of the underlying portion of the seal ring has little effect on stress because one is still left with the solder pulling on the edge of the seal ring, which results in the stress point. By terminating the solder short of the edge of the metal that adheres to the ROIC surface and providing an intervening layer, the stress relief buffer layer, of, for example, titanium, the abrupt edge that conducts the stress down to a localized region on the ROIC surface is terminated above the ROIC's surface and covered with a more ductile material. The inventors have further recognized that once the coincident edge is eliminated, thickening the underlying titanium layer either by thickening the stress relief buffer layer, in one embodiment, or thickening the titanium bonding material adhesion layer, in another embodiment, will further reduce stress, but only if the coincident edge is first eliminated.
In accordance with the disclosure, a structure is provided having: a substrate; a metal ring disposed on a surface portion of the substrate around a surface region of the substrate; a bonding material disposed on the metal ring, the bonding material having inner and outer edges; and wherein the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.
In one embodiment, a first layer of the metal ring includes a stress relief buffer layer disposed on the surface portion of the substrate, the first layer having a higher ductility than that of the surface portion at a predetermined temperature, \and a width greater than the width of the bonding material, the stress relief buffer layer extending laterally beyond at least one of the inner and outer edges of the bonding material.
In one embodiment, the stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.
In one embodiment, outer regions of a top surface of the metal ring comprise material inhibiting adhesion of the bonding material to the top surface, and wherein portions of the metal ring extend laterally beyond at least one of the inner and outer edges of the bonding material
In one embodiment, a bonding material masking layer on the top surface of the metal ring, the bonding material passing through a window in the masking layer exposing a portion of the top surface of the metal layer and wherein a portion of the bonding material passes through the window onto the exposed portion of the top surface of the metal layer.
In one embodiment, portions of the metal ring extend laterally beyond at least one of the inner and outer edges of the bonding material.
In one embodiment, a lid and wherein the bonding material bonds the substrate to the lid.
The stress relief buffer layer adheres effectively to the substrate and is not wetted by the bonding material. Furthermore, the stress relief buffer layer has a Coefficient of Thermal Expansion (CTE) preferably midway between the CTE of the surface portion of the substrate bonded to the stress relief buffer layer and the CTE of the solder or bonding material and has the property of a ductile material to locally yield in regions of high stress instead of fracturing as in the case of brittle materials such as SiON and Silicon. An exemplary stress relief buffer layer material is titanium.
With such an arrangement, stress produced between the substrate, for example, a semiconductor wafer and the adhesive layer is shifted from a point where the edge of the bonding material contacts the semiconductor wafer to a point where the edge of the bonding material contact the stress relief buffer layer and thus is shifted away from the semiconductor wafer and any associated overglass or brittle substrate material. Thus, the stress relief buffer layer serves as a stress reducing layer, shifting the region of high stress from the brittle overglass to the more ductile underlying layer.
More particularly, when using a solder having a high thermal contraction rate to bond and hermetically seal the two wafers to form the package, as the solder cools from its melted temperature it shrinks, inducing high levels of stress in the underlying semiconductor wafer at the edges of the solder joint. The use of the stress relief buffer layer 1 isolates the high stress region at the edge of the solder joint from the underlying brittle semiconductor wafer, interposing the material of the stress relief buffer layer having a higher level of ductility than the ductility of the semiconductor wafer, and a thermal contraction rate less than the solder yet higher than the underlying wafer. The stress relief buffer layer has a thermal expansion between that of the solder layer and the surface of the wafer and reduces the stress in the more brittle wafer. Thus, the disclosure enables the integration of a high CTE solder or other bonding material with a brittle overglass layer on a semiconductor structure. Further, the process may be used on the device wafer, lid or both.
It should be understood that the term ring-shaped refers to and includes shape enclosing a space; it may be circular, rectangular, square oval or may have an irregular shape, such as a serpentine or meandering shape.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.